802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS

by Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano

Abstract:

This paper presents an 802.11g/n compliant wakeup radio solution that consists of an innovative on-off keying (OOK) emulating orthogonal frequency division multiplexing (OFDM) modulation scheme, and a fully integrated, highly scaled, ultra-low power wake-up receiver design in 14-nm FinFET CMOS technology requiring only a 32-kHz real-time clock reference. The receiver achieves -72-dBm sensitivity and +20 dBr adjacent channel interference (ACI) rejection at 10-3 bit error rate (BER) while consuming 95 μW. This receiver can be utilized along with any legacy Wi-Fi transmitter without changing any hardware.

View PDF

Reference:

E. Alpman, A. Khairi, R. Dorrance, M. Park, V. S. Somayazulu, J. R. Foerster, A. Ravi, J. Paramesh, S. Pellerano, "802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS," IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 5, pp. 1411–1422, May 2018.

Bibtex Entry:

@ARTICLE{Alpman2018:JSSC,
    author    = {Alpman, Erkan and Khairi, Ahmad and Dorrance, Richard and Park, Minyoung and Somayazulu, V. Srinivasa and Foerster, Jeffrey R. and Ravi, Ashoke and Paramesh, Jeyanandh and Pellerano, Stefano},
    title     = {{802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS}},
    journal   = {IEEE Journal of Solid-State Circuits (JSSC)},
    year      = {2018},
    month     = {May},
    volume    = {53},
    number    = {5},
    pages     = {1411--1422},
    doi       = {10.1109/JSSC.2018.2817603},
    abstract  = {This paper presents an 802.11g/n compliant wakeup radio solution that consists of an innovative on-off keying (OOK) emulating orthogonal frequency division multiplexing (OFDM) modulation scheme, and a fully integrated, highly scaled, ultra-low power wake-up receiver design in 14-nm FinFET CMOS technology requiring only a 32-kHz real-time clock reference. The receiver achieves -72-dBm sensitivity and +20 dBr adjacent channel interference (ACI) rejection at 10-3 bit error rate (BER) while consuming 95 μW. This receiver can be utilized along with any legacy Wi-Fi transmitter without changing any hardware.},
    url       = {https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8345365}
}