by Deepak Dasalukunte, Richard Dorrance, Le Liang, Lu Lu
Abstract:
Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian methods. This work presents the hardware architecture and implementation of a vector processor for one such application, Bayesian channel estimation (CE) (BCE). The BCE vector processor supports a generic instruction set with a supplement of specialized instructions to realize Bayesian algorithms in the signal processing context. The vector processor is designed to work as an accelerator in a system-on-chip (SoC) with an AHB/AXI bus interface or as stand-alone unit. The vector processor achieves more than 4× improvement in performance when compared with a traditional CE algorithm running on a commercial vector processor. To the best of authors knowledge, this is a first known hardware implementation of a variational Bayesian inference algorithm for a wireless communication application.
Reference:
D. Dasalukunte, R. Dorrance, L. Liang, L. Lu, "A Vector Processor for Mean Field Bayesian Channel Estimation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 29, no. 7, pp. 1348–1359, July 2021.
Bibtex Entry:
@ARTICLE{Dasalukunte2021:TVLSI,
author = {Dasalukunte, Deepak and Dorrance, Richard and Liang, Le and Lu, Lu},
title = {{A Vector Processor for Mean Field Bayesian Channel Estimation}},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)},
year = {2021},
month = {July},
volume = {29},
number = {7},
pages = {1348--1359},
doi = {10.1109/TVLSI.2021.3077408},
abstract = {Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian methods. This work presents the hardware architecture and implementation of a vector processor for one such application, Bayesian channel estimation (CE) (BCE). The BCE vector processor supports a generic instruction set with a supplement of specialized instructions to realize Bayesian algorithms in the signal processing context. The vector processor is designed to work as an accelerator in a system-on-chip (SoC) with an AHB/AXI bus interface or as stand-alone unit. The vector processor achieves more than 4× improvement in performance when compared with a traditional CE algorithm running on a commercial vector processor. To the best of authors knowledge, this is a first known hardware implementation of a variational Bayesian inference algorithm for a wireless communication application.},
url = {hhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9434950}
}