Techniques for analog multibit data representation for in-memory computing

@PATENT{Dorrance2024:US12154638,
    author    = {Wang, Hechen and Dorrance, Richard and Liu, Renzhi and Dasalukunte, Deepak },
    title     = {{Techniques for analog multibit data representation for in-memory computing}},
    year      = {2024},
    month     = {November},
    day       = {26},
    number    = {US 12,154,638},
    type      = {Patent},
    location  = {US},
    gpatentid = {US12154638},
    abstract  = {Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.},
    url       = {}
}