Error-tolerant architecture for power-efficient computing

@PATENT{Dorrance2021:US10969431,
    author    = {Dorrance, Richard and Belogolovy, Andrey and Zhang, Xue and Wang, Hechen},
    title     = {{Error-tolerant architecture for power-efficient computing}},
    year      = {2021},
    month     = {April},
    day       = {6},
    number    = {US 10,969,431},
    type      = {Patent},
    location  = {US},
    gpatentid = {US10969431},
    abstract  = {A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.},
    url       = {}
}