A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications

by Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent Carlton

Abstract:

Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.

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Reference:

H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, N. Gowda, B. Carlton, "A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications," in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 1–2, June 2024.

Bibtex Entry:

@INPROCEEDINGS{Wang2024:VLSI,
    author    = {Wang, Hechen and Liu, Renzhi and Dorrance, Richard and Dasalukunte, Deepak and Gowda, Niranjan and Carlton, Brent},
    title     = {{A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications}}, 
    booktitle = {2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}, 
    year      = {2024},
    month     = {June},
    pages     = {1--2},
    doi       = {10.1109/VLSITechnologyandCir46783.2024.10631356},
    abstract  = {Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.},
    url       = {https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10631356}
}