| [C20] | H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, N. Gowda, B. Carlton, "A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications," in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 1–2, June 2024.
|
| [C19] | R. Dorrance, D. Dasalukunte, H. Wang, R. Liu, B. Carlton, "Energy Efficient BNN Accelerator using CiM and a Time-Interleaved Hadamard Digital GRNG in 22nm CMOS," in 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 2–4, November 2022.
|
| [C18] | R. Camacho, G. Fabila, L. Gonzalez, J. Felip, M. Subedar, P. Mendoza, J. Romero, A. Pedroza, R. Dorrance, D. Dasalukunte, "An Accelerator for Emerging AI Workloads at the Edge,” in Design and Test Technology Conference ," in Design and Test Technology Conference (DTTC'22), pp. 1–4, September 2022.
|
| [C17] | H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, B. Carlton, "C-2C Ladder Based 8-bit Charge Domain Compute-in-Memory Achieving 32.2 TOPS/W Efficiency for Edge Artificial Intelligence," in Design and Test Technology Conference (DTTC'22), pp. 1–4, September 2022.
|
| [C16] | H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, X. Liu, D. Lake, B. Carlton, M. Wu, "A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference," in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 36–37, June 2022.
|
| [C15] | R. Liu, B. K. T. Asma, R. Dorrance, T. Cox, R. Jain, T. Acikalin, Z. Zhou, T. Yang, J. Escobar-Pelaez, S. Yamada, K. Foust, B. Carlton, "A 2Gb/s 9.9pJ/b Sub-10GHz Wireless Transceiver for Reconfigurable FDD Wireless Networks and Short-Range Multicast Applications," in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC'22), pp. 263–266, June 2022.
|
| [C14] | J. Chen, W. Wong, B. Hamdaoui, A. Elmaghbub, K. Sivanesan, R. Dorrance, L. L. Yang, "An Analysis of Complex-Valued CNNs for RF Data-Driven Wireless Device Classification," in IEEE International Conference on Communications (ICC'22), pp. 4318–4323, May 2022.
|
| [C13] | R. Dorrance, A. Belogolovy, H. Wang, X. Zhang, "A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs," in 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), pp. 341–346, September 2020.
|
| [C12] | R. Dorrance, R. Liu, K. Asma Beevi, D. Dasalukunte, M. A. S. Lopez, V. Kristem, S. Azizi, B. Carlton, "An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba," in Proceedings of the 2019 Symposium on VLSI Circuits (VLSI'19), pp. C80–C81, June 2019.
|
| [C11] | R. Liu, A. B. K. T., R. Dorrance, D. Dasalukunte, M. A. Santana Lopez, V. Kristem, S. Azizi, M. Park, B. R. Carlton, "An 802.11ba 495μW -92.6dBm-Sensitivity Blocker-Tolerant Wake-up Radio Receiver Fully Integrated with Wi-Fi Transceiver," in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC'19), pp. 255–258, June 2019.
|
| [C10] | R. Dorrance, A. Belogolovy, H. Wang, X. Zhang, "Error Tolerant Architectures for Power Efficient Computing and Communications," in Design and Test Technology Conference (DTTC'19), pp. 1–8, May 2019.
|
| [C9] | T. Karnik, D. Kurian, P. Aseron, R. Dorrance, E. Alpman, A. Nicoara, R. Popov, L. Azarenkov, M. Moiseev, L. Zhao, S. Ghosh, R. Misoczki, A. Gupta, M. Akhila, S. Muthukumar, S. Bhandari, Y. Satish, K. Jain, R. Flory, C. Kanthapanit, E. Quijano, B. Jackson, H. Luo, S. Kim, V. Vaidya, A. Elsherbini, R. Liu, F. Sheikh, O. Tickoo, I. Klotchkov, M. Sastry, S. Sun, M. Bhartiya, A. Srinivasan, Y. Hoskote, H. Wang, V. De, "A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS," in Proceedings of the International Solid-State Circuits Conference (ISSCC'18), pp. 46–48, February 2018.
|
| [C8] | R. Dorrance and D. Marković, "A 190GFLOPS/W DSP for Energy-Efficient Sparse-BLAS in Embedded IoT," in Proceedings of the 2016 Symposium on VLSI Circuits (VLSI'16), pp. 182–183, June 2016.
|
| [C7] | R. Dorrance, F. Ren, and D. Marković, "A Scalable Sparse Matrix-Vector Multiplication (SpMxV) Kernel For Sparse-BLAS on FPGAs," in Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA'14), pp. 161–170, February 2014.
|
| [C6] | F. Ren, R. Dorrance, W. Xu, D. Marković, "A Single-Precision Compressive Sensing Signal Reconstruction Engine on FPGAs," in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL'13), pp. 1–4, September 2013.
|
| [C5] | R. Dorrance, J. G. Alzate, S. S. Cherepov, P. Upadhyaya, K. L. Wang, P. K. Amiri, D. Marković, "Voltage-controlled MRAM for 3D Stackable Non-Volatile Memories," in Proceedings of the International Solid-State Circuits Conference Student Research Preview (ISSCC'13), February 2013.
|
| [C4] | J. G. Alzate, P. K. Amiri, P. Upadhyaya, S. S. Cherepov, J. Zhu, M. Lewis, R. Dorrance, J. A. Katine, J. Langer, K. Galatsis, D. Marković, I. Krivorotov, K. L. Wang, "Voltage-Induced Switching of Nanoscale Magnetic Tunnel Junctions," in Proceedings of the International Electron Devices Meeting (IEDM'12), pp. 29.5.1–29.5.4, December 2012.
|
| [C3] | F. Ren, H. Park, R. Dorrance, Y. Toriyama, C. K. Yang, D. Marković, "A Body-Voltage-Sensing-Based Short Pulse Reading Circuit for Spin-Torque Transfer RAMs (STT-RAMs)," in Proceedings of 13th International Symposium on Quality Electronic Design (ISQED'12), pp. 275–282, March 2012.
|
| [C2] | H. Park, R. Dorrance, A. A. Hafez, F. Ren, D. Marković, C. K. Yang, "Analysis of STT-RAM Cell Design with Multiple MJTs Per Access," in Proceedings of the ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'11), pp. 53–58, June 2011.
|
| [C1] | R. Dorrance, F. Ren, Y. Toriyama, A. A. Hafez, C. K. Yang, D. Marković, "Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell," in Proceedings of the ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'11), pp. 32–36, June 2011.
|